Transistor device and method for manufacturing the same

ABSTRACT

A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect.

The present application claims priority under 35 U.S.C. 119 and 35U.S.C. 365 to Korean Patent Application No. 10-2005-0133428 (filed onDec. 29, 2005), which is hereby incorporated by reference in itsentirety.

BACKGROUND

When a transistor of a semiconductor device is formed, a structure of agate may soar relatively high over a silicon substrate. This may createproblems in defining the length of the gate when the devices are scaleddown. Also, when lightly doped drain ion implants and source and drainion implants are formed, masking steps are required. Thus the cost forfabricating the devices is increased.

Therefore, there has been a need to create a transistor device having anew gate structure.

SUMMARY

Embodiments relate to semiconductor device, and more particularly, to amethod for fabricating a transistor that may overcome a short channeleffect(SCE).

Accordingly, embodiments are directed to a transistor device and amethod for manufacturing the same that substantially obviates one ormore problems due to limitations and disadvantages of the related art.

Embodiments relate to a transistor device and a method for manufacturingthe same, which effectively may reduce size of a semiconductor device.

Additional advantages, objects, and features of the embodiments will beset forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theembodiments. The objectives and other advantages of the embodiments maybe realized and attained by the structure particularly pointed out inthe written description and claims hereof as well as the appendeddrawings.

Embodiments relate to a method for fabricating a transistor by forming afirst insulation layer and a second insulation layer over asemiconductor substrate; selectively etching the first and secondinsulation layers and semiconductor substrate to form a recess;depositing a gate insulation layer and a gate conductor layer;planarizing the gate insulation layer and the gate conductor layer toform a gate structure filling the recess; removing the second insulationlayer; forming a spacer over a side wall of the gate; implanting ionsinto the semiconductor substrate near the spacer to form source anddrain regions; wet etching the second insulation layer and the gateinsulation layer to expose an upper side wall of the gate and upperportions of the source and drain regions; and forming a salicide layeron the exposed surface of the gate and over the source and drainregions.

The planarizing may be carried out by chemical mechanical polishing(CMP) of the gate conductor using the second insulation layer as apolishing stop layer.

The LDD and the source and drain ion implantation profile may be formedby ion implantation using a mask once in the source and drain regions.The gate conductor may include polysilicon, and the gate insulationlayer may include nitride-based oxide, hafnium-based oxide,tantalum-based oxide, or titanium-based oxide.

The recess may be etched to a depth of 500 Å to 2000 Å.

The wet etching of the second insulation layer leaves a portion of thesecond insulation layer which is over the source and drain regions,adjacent the gate insulation layer and below the spacer. The spacerentirely covers and extends beyond the top surface of the secondinsulation layer.

Embodiments relate to a transistor device including a recess in asurface of semiconductor substrate; a gate insulation layer formed overan inner side of the recess; a gate conductor filling the recess inwhich the gate insulation layer is formed; and source and drain regionslocated over the substrate adjacent the recess. An upper portion of thegate conductor projects above the surface of the semiconductorsubstrate. A spacer may be formed over the side wall of a gateinsulation portion that is projected above the surface of semiconductorsubstrate. A salicide layer may be formed over a upper portion of thegate and over the source and drain regions.

Embodiments relate to a transistor device and a method for manufacturingthe same, which effectively may reduce size of a semiconductor device.

It is to be understood that both the foregoing general description andthe following detailed description of the embodiments are exemplary andexplanatory and are intended to provide further explanation of theclaimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 7 are sectional views illustrating a transistor deviceand a method for fabricating the same according to embodiments.

DETAILED DESCRIPTION

With reference to FIG. 1, a first insulation layer 3 and a secondinsulation layer 5 are deposited over a semiconductor substrate 1. Afirst photoresist mask layer 100 is formed over the insulating layersfor etching the first insulation layer 3 and the second insulation layer5. First insulation layer 3 may be composed of silicon oxide while thesecond insulation layer 5 may be composed of silicon nitride.

In FIG. 2, the first and the second insulation layer 3 and 5 areselectively etched using mask 100 to create patterns 3′ and 5′, whichcollectively constitute etching mask 6. A dry etching process using mask6 forms recess 2 in the semiconductor substrate 1. The recess 2 may beetched to a depth of approximately 500 Å to 2000 Å.

In FIG. 3, a gate insulation layer 7 and a gate conductor layer aredeposited. A gate 9 and the gate insulation layer 7 are planarized usinga chemical mechanical polishing (CMP) method using the pattern of thesecond insulation layer 5′ as a stop layer. Therefore, gate 9, whichfills recess 2, is approximately 500 Å to 2000 Å thick. The gate 9 mayinclude polysilicon and the gate insulation layer may include anitride-based oxide, hafnium-based oxide, tantalum-based oxide, ortitanium-based oxide.

In FIG. 4, the pattern of the insulation layer 5′ has been completelyremoved using, for example, a wet etching method using phosphoric acidsolution.

With reference to FIG. 5, after depositing a layer for the spacer 11over the side wall of the gate 7, spacer 11 is formed by using, forexample, a front etching method. The spacer 11 may also be formed by anisotropic etching method. And then LDD and high density source and drainregions 13′ are formed by implanting ions. The ion implantation processis performed once at the LDD and source and drain regions 13′ to form aprofile of the LDD and source/drain regions 13′. The ion implant profileafter annealing is shown.

In FIG. 6, a gate insulation layer 7′ and a second pattern 3″ of thefirst insulation layer are formed by wet etching. The second pattern 3″of the first insulation layer forms a recessed filler over the gateinsulation layer 7′ between the spacer 11 and LDD region. Gateinsulation 7′ is recessed from the top plane of the gate and spacers 11,to expose an upper side wall of the gate 9.

In FIG. 7, a salicide process is performed on gate 9, and source anddrain regions 13 to form salicide layer 15. The salicide layer 15 isformed by heat treatment between 700 to 1000 ° C., after depositing oneof, for example, cobalt, nickel, and Ti over the whole surface.

As described, embodiments relate to a method for fabricating asemiconductor transistor. A new scheme, facilitating a scaling down ofthe size of the transistors, is proposed. The gate resistance may bereduced without increasing the area used on the surface of thesubstrate. Lateral diffusion of the ion implant source may be moreeasily controlled to reduce the short channel effect. It is thereforepossible to implement a shallow well ion implantation process at asmaller device scale, with smaller transistor features.

It will be obvious and apparent to those skilled in the art that variousmodifications and variations can be made in the embodiments disclosed.Thus, it is intended that the disclosed embodiments cover the obviousand apparent modifications and variations, provided that they are withinthe scope of the appended claims and their equivalents.

1-8. (canceled)
 9. A transistor device comprising: a semiconductorsubstrate having a recess; a gate insulation layer covering the bottomand sides of the recess; a gate conductor filling the recess andprojected over the semiconductor substrate; a spacer over the uppersidewall of the gate; source and drain regions formed over thesemiconductor substrate near the spacer; and a salicide layer formedover the gate, and the source and drain regions.
 10. A transistor devicecomprising: a recess in a surface of semiconductor substrate; a gateinsulation layer formed over an inner side of the recess; a gateconductor filling the recess in which the gate insulation layer isformed; and source and drain regions located over the substrate adjacentthe recess.
 11. A transistor device according to claim 10, wherein anupper portion of the gate conductor projects above the surface of thesemiconductor substrate.
 12. A transistor device according to claim 11,wherein a spacer is formed over the side wall of a gate insulationportion that is projected above the surface of semiconductor substrate.13. A transistor device according to claim 10, wherein a salicide layeris formed over a upper portion of the gate and over the source and drainregions.
 14. A transistor device according to claim 10, wherein the gateregion is made of polysilicon.
 15. A method according to claim 10,wherein the gate insulation layer includes one selected from the groupconsisting of nitride-based oxide, hafnium-based oxide, tantalum-basedoxide, and titanium-based oxide.
 16. An apparatus comprising: asemiconductor substrate having a recess formed therein; a gate formed inand protruding from the recess; insulating layer patterns formed oversidewalls of the gate such that an uppermost surface of the gateprojects above the uppermost surface of the insulating layer patterns;spacers formed over the sidewalls of the gate such that an uppermostsurface of the spacers projects above the uppermost surface of the gate;and a salicide layer formed on the uppermost surface and also theuppermost sidewalls of the gate.
 17. The apparatus of claim 16, whereinthe insulating layer patterns are composed of an oxide material.
 18. Theapparatus of claim 17, wherein the oxide material comprises siliconoxide.
 19. The apparatus of claim 16, wherein the recess has a depth ofapproximately 500 Å to 2000 Å.
 20. The apparatus of claim 16, whereinthe gate is composed of polysilicon.
 21. The apparatus of claim 16,further comprising a gate insulation layer formed in the recess andunder the gate.
 22. The apparatus of claim 21, wherein the gateinsulation layer is recessed from the uppermost surface of the gate toexpose the upper sidewalls of the gate.
 23. The apparatus of claim 21,wherein the gate insulation layer is composed of one selected from thegroup consisting of nitride-based oxide, hafnium-based oxide,tantalum-based oxide, and titanium-based oxide.
 24. The apparatus ofclaim 16, further comprising lightly doped drain and source and drainregions formed in the semiconductor substrate adjacent to the recess.25. The apparatus of claim 24, further comprising second salicide layersformed on the lightly doped drain and source and drain regions.
 26. Theapparatus of claim 25, wherein the second salicide layers are composedof one of cobalt, nickel and titanium.
 27. The apparatus of claim 16,wherein a portion of the salicide layers are formed on the gateinsulating layer.
 28. The apparatus of claim 16, wherein the salicidelayers are composed of one of cobalt, nickel and titanium.